Toshiba TC9349AFG Manual page 12

PIN No. Symbol Pin Name
P8-0/VDET
(BRK13) /Detected doubler
voltage input
P8-1/SI2 /Serial data input 2
/DDCK1 /Doubler clock output 1
(BRK14)
58 ~ 61
P8-2/SCK2 /Serial clock input/
/RX2
(BRK15) /UART input 2
P8-3/SDIO2 /Serial clock input/
/TX2
(BRK16) /UART output 2
RESET
62 Reset input
Function and Operation
The port 8 is a 4-bit N-ch open-drain I/O
port, allowing control of ON/OFF for an
output transistor to be programmed in 1-bit
units When an output is set as OFF, the
pin can be used as an input port.
When the backup release enable state is
set, the backup state in the clock stop and
wait modes can be released by a change
in the input or output pin.
The I/O port is N-ch open-drain I/O. Up to
5.5 V can be input to or output from the I/O
port.
This pin is used to configure the switching
regulator for VT.
The voltage is doubled by the doubler
clock output DDCK1 (P8-1) or DDCK2
(P9-2). The divided voltage is input to the
I/O port 8
detected doubler voltage VDET pin (P8-0)
to control the doubler clock.
The DDCK1 output is 5.5V N-ch output.
The VT doubled voltage is doubled to 5 V
through the use of an external transistor.
The DDCK2 output is CMOS output The
voltage can be doubled through the use of
output 2
an external transistor.
For the doubler clock, it is possible to
select from three types of dividing
output 2
frequency: crystal oscillator, high-speed
oscillator and OSCin input.
It is also possible to select through
programming the comparator reference
potential of the VDET input: either 0.75 V
or 1.0 V.
Pins P8-1 to P8-3 are used as serial
interface circuit (SIO) input/output pins.
The serial interface circuit corresponds to
2-wired type, 3-wired type, and UART.
Serial clock edge, serial clock input/output,
and clock frequency can be selected,
facilitating the control of various LSIs and
communication between controllers.
When interrupts of a serial interface circuit
are enabled, an interrupt is generated after
serial interface and the program jumps to
the 3rd address.
Input pin for system reset signals. The
input uses built-in Schmitt circuit.
RESET
takes place while at Low level; at
High level, the program starts from
address "0" after 100 ms standby.
Normally, if voltage is applied to the VCPU
pin, the system is reset (power-on
reset).Therefore, this pin should be set to
High level during operation.
12
TC9349AFG
Remarks
Detected
doubler
voltage input
V
DD
Input instruction
Release enables
(P8-0)
V
DD
Input instruction
Release enables
(P8-1, P8-3)
V
CPU
2006-02-24