Y2 Y4 Y8 - Toshiba TC9349AFG Manual

Stack register
The stack register consists of an address stack register (ASR) and an interruption stack register (ISR). A stack register is
used when subroutine call instructions and interrupt processing are executed. Interrupt stack registers comprise 26 G-
register, data select, carry flag, and data register bits, as described in the register port item and I/O map. These stack
registers are arranged on an I/O map, and are read from and written into with input and output instructions.
1. Address stack register (ASR)
The address stack register (ASR) is a 14 bit × 16 page register. When the subroutine call instruction and the interrupt
processing are executed, the value increased by +1 of the content of the program counter, i.e., the return address, is stored in
the address stack register. When interrupt processing is executed, a return address that is an interrupt processing execution
address is stored in the address stack register. This register consists of 16 pages and is specified by four address stack
pointer (ASP) bits. If transmitted to an address stack, an address stack pointer will be adjusted by -1. Then, after processing
of the subroutine or interrupt, the address stack pointer is increased by +1 with the RN/RNS instruction or the RNI
instruction, the content of the address stack register is transmitted to the program counter, and the program returns from the
subroutine or the interrupt processing.
An address stack register comprises 16 pages and features 16 nesting levels.
The address stack register and the address stack pointer are arranged on the I/O map, and their contents can be referred to
or rewritten.
φL/K10(0)
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ASP ASP ASP ASP
0 1 2 3
Address stack pointer
φL/K10(2)
φL/K10(3)
φL/K10(4)
φL/K10(5)
Page 0
Page 1
Page 1
Page 2
Page 3
Note: The program memory area consists of 16 kilobytes, and 13 bits are used. Therefore set the most
significant bit (ASR13) to "0".
At the time of CAL instruction / interrupt processing execution
At the time of CAL instruction / interruption processing execution
At the time of RN/RNS/RNI instruction processing execution
Address stack register
Address stack register
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ASR0 ASR1 ASR2 ASR3
ASR4 ASR5 ASR6 ASR7
ASR8 ASR9 ASR10 ASR11
ASR12 ASR13 */0 */0
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Page 15
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45
(ASP)←ASP+1
(ASP)←ASP-1
At the time of CAL instruction /
At the time of CAL instruction /
interrupt processing execution
interruption processing execution
ASR←(PC)+1
PC←(ASR)
At the time of RN/RNS/RNI
instruction processing execution
TC9349AFG
Program memory
area
（ROM）
(ROM)
2006-02-24