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Interrupt function
There are six types of peripheral hardware for which the interrupt function can be utilized: the INTR1 terminal, the
INTR2 terminal, the timer port, the serial interface, the timer counter, and the decreased voltage detection circuit.
This peripheral hardware will issue an interrupt request signal if certain conditions are satisfied. On reception of an
interrupt, the data for the G-register, data selection, carry flag, and data register are shunted to an interrupt stack register,
and the return address is shunted to the address stack register. The process then branch to the vector address determined by
the various interrupt factors and starts the related interrupt processing routine.
The interrupt routine requires preprocessing and post-processing to enable recovery of the same operational state that
prevailed when the interrupt occurred. On interrupt, the G-register, data selection, carry flag, and data register are
automatically shunted to the interrupt stack register; they are returned from the interrupt stack register on execution of the
return instruction for interrupt (RNI). Registers used with other ALU and memory data that cannot be broken must be
shunted to and recovered from the data memory for interrupt through the use of programming.
Interrupt priority can be set through programming. During interrupt processing, processing of an interrupt with a priority
lower than the interrupt currently being processed is prohibited.
The data of the interrupt stack register and the address stack register return on executing of the return instruction for
interrupt (RNI), and the interrupt processing ends.
1. Interrupt control circuit
The interrupt control circuit consists of an interrupt enable flag, interrupt latch, and interrupt priority circuit block. These
performs are set and controlled with OUT2/IN2 instructions.
(1)
Interrupt enable flags
The interrupt enable flags consist of individual enable flags corresponding to the four interrupt factors, and a
master enable flag, which permits and prohibits the whole interrupt processing. The individual enable flags permit
and prohibit interrupt corresponding to each interrupt factor. The enable registers of these flags indicate permission if
set to "1", prohibition if reset to "0".
An individual enable flag is accessed with OUT2/IN2 instructions for which [CN = 0H] has been specified in the
operand.
The interrupt master enable flag sets interrupt permission and prohibition. On execution of the EI instruction, the
master enable flag is set to "1" and interrupt is permitted. On execution of the DI instruction, the master enable flag is
reset to "0" and interrupt is prohibited. When an interrupt request permitted by the individual enable flag is issued in
the interrupt-enabled state, the CPU receives the interrupt and, by branching to the different vector addresses,
executes the interrupt routine. In interrupt reception processing and interrupt return processing, the master enable flag
is in the hold state. When all other interrupts are to be prohibited during interrupt processing, therefore, the DI
instruction is executed and interrupt is prohibited.
The interrupt master flag can be read into a data memory by an IN2 instruction for which [CN = 2H] is specified in
the operand.
Y1
Y2
φLK20
EF1
EF2
Individual enable flag:
Y1
Y2
φK22
IMF
0
Master enable flag
Note: Do not change the setting of the individual enable flag during interrupt processing.
Y4
Y8
EF3
EF4
EF1･･･INTR1 pin
EF2･･･INTR2 pin / Timer port
EF3･･･Serial interface / Timer port /
Decreased voltage detection
EF4･･･8 bit timer counter
Y4
Y8
0
0
Reset to "0" on acceptance of interrupt or on execution of the DI instruction.
Reset to "1" on execution of the RNI or of the EI instruction.
48
TC9349AFG
"0" ･･･Prohibition
"1" ･･･Enable
2006-02-24
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