HP 16600A Series User Manual page 132

Mnemonic Name
GND Ground
BKPT Breakpoint
DSCLK Development
system clock
FREEZE Freeze
QUOT Quotient out
RESET Reset
IFETCH Instruction fetch
DSI Development
serial in
V
DD
IPIPE Instruction pipe
DSO Development
serial out
DS Data strobe
BERR Bus error
The following signals should be available at the BDM port:
BDM signal definitions
Direction
Input
(to target)
Input
Output
Output
Output
Output
Input
Output
Output
Output
Output
Input
Solutions for CPU32
Chapter 6: Connecting and Configuring the Emulation Module
Designing a Target System for the Emulation Module
Signal Description
Signals a hardware breakpoint. Also used to
place the CPU32 in background debug mode.
Active low
Serial input clock
Indicates BDM mode
Quotient bit of the polynomial divider. Not used in
BDM mode.
Indicates system reset
Indicates when the CPU is performing an
instruction word prefetch and when the
instruction pipeline has been flushed (active low)
BDM data input
Target power (+5 V or +3.3 V)
Used to track the movement of words through the
instruction pipeline (active low)
BDM data output
During read, indicates ready to receive valid data;
during write
Used to terminate target memory cycles (optional)
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