HP 16600A Series User Manual page 212

Chapter 9: Using the Analysis Probe and Emulation Module Together
Triggering the Logic Analyzer from the
Emulation Module
You can create an intermodule measurement which will allow the
emulation module to trigger another module such as a timing analyzer
or oscilloscope.
If you are only using a state analyzer to capture the processor bus then
it will be much simpler to use "Tracing until processor halts" as
described on page 210.
Before you trigger a logic analyzer (or another module) from the
emulation module, you should understand a few things about the
emulation module trigger:
The emulation module trigger signal
The trigger signal coming from the emulation module is an "In
Background Debug Monitor" ("In Monitor") signal. This may cause
confusion because a variety of conditions could cause this signal and
falsely trigger your analyzer.
The "In Monitor" trigger signal can be caused by:
• The most common method to generate the signal is to click
Break
click in the Emulation Control Interface. Going from "Run"
(Running User Program) to "Break" ("In Monitor") generates the trigger
signal.
• Another method to generate the "In Monitor" signal is to click
Break
then click . Going from the reset state of the processor to the "In
Monitor" state will generate the signal.
• In addition, an "In Monitor" signal is generated any time a debugger or
other user interface reads a register, reads memory, sets breakpoints or
steps. Care must be taken to not falsely trigger the logic analyzers listening
to the "In Monitor" signal.
Solutions for CPU32
Triggering the Logic Analyzer from the Emulation Module
Run
and then
Reset
and
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