Control Register Settings For Ppg Output Operation - NEC 78K0 User Manual

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-18. Control Register Settings for PPG Output Operation
7 6 5
TMC0n 0 0 0
7 6 5
CRC0n 0 0 0
7 OSPT0n OSPE0n
TOC0n 0 0 0
ES1n1 ES1n0 ES0n1
PRM0n 0/1 0/1 0/1
Cautions 1. Values in the following range should be set in CR00n and CR01n:
0000H ≤ CR01n < CR00n ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR00n setting value + 1) has a duty of
(CR01n setting value + 1)/(CR00n setting value + 1).
Remark ×: Don't care
µ
n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
(a) 16-bit timer mode control register 0n (TMC0n)
4 TMC0n3 TMC0n2 TMC0n1 OVF0n
0 1 1 0
(b) Capture/compare control register 0n (CRC0n)
4 3 CRC0n2 CRC0n1 CRC0n0
×
0 0 0
(c) 16-bit timer output control register 0n (TOC0n)
TOC0n4 LVS0n LVR0n TOC0n1 TOE0n
1 0/1 0/1 1
*
(d) Prescaler mode register 0n (PRM0n)
ES0n0 3 2 PRM0n1 PRM0n0
0/1 0 0 0/1
User's Manual U15947EJ2V0UD
0
Clears and starts on match between TM0n and CR00n.
0
CR00n used as compare register
CR01n used as compare register
1
Enables TO0n output.
Inverts output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting "11" is prohibited).
Inverts output on match between TM0n and CR01n.
Disables one-shot pulse output.
0/1
Selects count clock.
Setting invalid (setting "10" is prohibited.)
Setting invalid (setting "10" is prohibited.)
189