NEC 78K0 User Manual page 210

(6) Operation of OVF0n flag
<1> The OVF0n flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start occurs on a match between
TM0n and CR00n, the mode in which clear & start occurs at the TI0n valid edge, or the free-running mode
CR00n is set to FFFFH
TM0n is counted up from FFFFH to 0000H.
<2> Even if the OVF0n flag is cleared before the next count clock (before TM0n becomes 0001H) after the
occurrence of TM0n overflow, the OVF0n flag is re-set newly and clear is disabled.
(7) Conflicting operations
Conflict between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and capture trigger
input (CR00n/CR01n used as capture register)
Capture trigger input has priority. The data read from CR00n/CR01n is undefined.
Count clock
TM0n count value
Edge input
INTTM01n
Capture read signal
CR01n capture value
µ
Remark n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
210
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
↓
↓
Figure 7-41. Operation Timing of OVF0n Flag
Count clock
CR00n FFFFH
TM0n
FFFEH
OVF0n
INTTM00n
Figure 7-42. Capture Register Data Retention Timing
N N + 1
X
User's Manual U15947EJ2V0UD
FFFFH 0000H 0001H
*
N + 2 M
N + 2
Capture
M + 1 M + 2
M + 1
Capture, but
read value is
not guaranteed