NEC 78K0 User Manual page 474

(CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
Normal
operation
CPU operation
X1 input clock
Ring-OSC clock
(CPU clock)
CLME
Clock monitor status
Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
(6) Clock monitor status after X1 input clock oscillation is stopped by software
CPU operation
X1 input clock
Ring-OSC clock
MSTOP or
Note
MCC
CLME
Clock monitor status
Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input
clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time.
Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time.
Note The register that controls oscillation of the X1 input clock differs depending on the type of the clock supplied
to the CPU.
• When CPU operates on Ring-OSC clock:
• When CPU operates on subsystem clock: Controlled by bit 7 (MCC) of the processor clock control
474
CHAPTER 23 CLOCK MONITOR
Figure 23-3. Timing of Clock Monitor (3/4)
(5) Clock monitor status after STOP mode is released
Clock supply
stopped
STOP
Oscillation Oscillation stabilization time
stopped (time set by OSTS register)
17 clocks
Monitoring Monitoring stopped
stopped
Normal operation (Ring-OSC clock or subsystem clock
Oscillation Oscillation stabilization time
stopped (time set by OSTS register)
Monitoring Monitoring stopped
stopped
User's Manual U15947EJ2V0UD
*
Controlled by bit 7 (MSTOP) of the main OSC control
register (MOC)
register (PCC)
Normal operation
Monitoring
Note
)
Monitoring