Format Of Automatic Data Transfer Interval Specification Register 0 (Adti0) - NEC 78K0 User Manual

(6) Automatic data transfer interval specification register 0 (ADTI0)
This is an 8-bit register used to specify the interval time between 1-byte communications during automatic
data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1).
Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave
mode). Setting in 1-byte communication mode (bit 6 (ATE0) of CSIMA0 = 0) is also valid. When the interval
time specified by ADTI0 after the end of 1-byte communication has elapsed, an interrupt request signal
(INTACSI) is output. The number of clocks for the interval can be set to between 0 and 63 clocks.
This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial
status register 0 (CSIS0) is 1, rewriting ADTI0 is prohibited.
Figure 17-8. Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0)
Address: FF95H After reset: 00H
Symbol 7
ADTI0
0
Caution Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes
priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is
generated even when ADTI0 is cleared to 00H.
Example Interval time when busy signal is not generated
<1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated
<2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated
<3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated
Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer.
The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by
an integer value.
Example When ADTI0 = 03H
SCKA0
388
CHAPTER 17 SERIAL INTERFACE CSIA0
R/W
6 5 4
0 ADTI05 ADTI04
Interval time of 3 clocks
User's Manual U15947EJ2V0UD
3 2
ADTI03 ADTI02
*
1 0
ADTI01 ADTI00