Pd780146, 780148, And 78F0148 Only) - NEC 78K0 User Manual

Figure 16-2. Block Diagram of Serial Interface CSI11 (
SI11/P03
Transmit data
controller
f /2
X
2
f /2
X
3
f /2
X
4
f /2
X
5
f /2
X
6
f /2
X
7
f /2
X
SCK11/P04
(1) Transmit buffer register 1n (SOTB1n)
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial
operation mode register 1n (CSIM1n) is 1.
The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and
output to the serial output pin (SO1n).
SOTB1n can be written or read by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication).
2. The SSI11 pin can be used in the slave mode. For details of the transmission/reception
operation, see 16.4.2 (2) Communication operation.
(2) Serial I/O shift register 1n (SIO1n)
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n)
is 0.
During reception, the data is read from the serial input pin (SI1n) to SIO1n.
RESET input clears this register to 00H.
Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication).
2. The SSI11 pin can be used in the slave mode. For details of the reception operation, see
16.4.2 (2) Communication operation.
µ
Remark n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
360
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Internal bus
8
Serial I/O shift
Transmit buffer
register 11 (SIO11)
register 11 (SOTB11)
Output latch
Transmit controller
Clock start/stop controller &
clock phase controller
User's Manual U15947EJ2V0UD
µ

PD780146, 780148, and 78F0148 Only)

8
Output
selector
INTCSI11
*
SO11/P02
Output latch
(P02)
SSI11
PM02