Automatic Transmission/Reception Mode Operation Timings - NEC 78K0 User Manual

8-bit single-chip microcontrollers
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At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0.
If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read
automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already
been transferred and re-execute transfer by performing (a) and (b) in (2) Automatic transmit/receive
data setting.
In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and
STB0/P145 pins can be used as ordinary I/O port pins.
Figure 17-13 shows the operation timing in automatic transmission/reception mode and Figure 17-14
shows the operation flowchart. Figure 17-15 shows the operation of internal buffer RAM when 6 bytes of
data are transmitted/received.
Figure 17-13. Automatic Transmission/Reception Mode Operation Timings
SCKA0
SOA0
D7 D6 D5 D4 D3 D2 D1 D0
SIA0
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF
TSF0
Cautions 1. Because,
transmit/receive function writes/reads data to/from the internal buffer RAM after 1-
byte
transmission/reception. As the buffer RAM write/read is performed at the same time
as CPU processing, the interval is dependent upon the value of automatic data
transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4
(STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5)
transmit/receive interval time).
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer
RAM by serial interface CSIA0 during the interval period, the interval time specified
by automatic data transfer interval specification register 0 (ADTI0) may be extended.
Remark
ACSIIF: Interrupt request flag
TSF0:
CHAPTER 17 SERIAL INTERFACE CSIA0
Interval
*
in
the
automatic
transmission/reception,
Bit 0 of serial status register 0 (CSIS0)
User's Manual U15947EJ2V0UD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
transmission/reception
an
interval
is
inserted
mode,
the
automatic
until
the
next
Automatic
399

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