(In Automatic Transmission/Reception Mode) (1/2 - NEC 78K0 User Manual

8-bit single-chip microcontrollers
Hide thumbs Also See for 78K0:
Table of Contents

Advertisement

CHAPTER 17 SERIAL INTERFACE CSIA0
In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1) in automatic transmission/reception
mode, internal buffer RAM operates as follows.
(i) Starting transmission/reception (see Figure 17-15 (a).)
When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred
from the internal buffer RAM to SIOA0. When transmission of the first byte is completed, receive
data 1 (R1) is transferred from SIOA0 to the buffer RAM, and automatic data transfer address count
register 0 (ADTC0) is incremented. Then transmit data 2 (T2) is transferred from the internal buffer
RAM to SIOA0.
(ii) 4th byte transmission/reception point (see Figure 17-15 (b).)
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the
internal buffer RAM to SIOA0. When transmission of the fourth byte is completed, the receive data 4
(R4) is transferred from SIOA0 to the internal buffer RAM, and ADTC0 is incremented.
(iii) Completion of transmission/reception (see Figure 17-15 (c).)
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOA0 to
the internal buffer RAM, and the interrupt request flag (ACSIIF) is set (INTACSI generation). Bit 0
(TSF0) of serial status register 0 (CSIS0) is cleared.
Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception

(in Automatic Transmission/Reception Mode) (1/2)

FA1FH
FA05H
Transmit data 6 (T6)
Transmit data 5 (T5)
Transmit data 4 (T4)
Transmit data 3 (T3)
Transmit data 2 (T2)
FA00H
Transmit data 1 (T1)
(a) Starting transmission/reception
*
User's Manual U15947EJ2V0UD
Receive data 1 (R1)
SIOA0
5
ADTP0
+1
0
ADTC0
0
ACSIIF
401

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

78kf1

Table of Contents