Data Assurance For Accessing Cpu Buffer Memory - Mitsubishi Electric MELSEC iQ-R Series User Manual

Data assurance for accessing CPU buffer memory

The methods for data assurance when accessing CPU buffer memory are as follows:
This product does not support CPU number-based data assurance; therefore, the data inconsistency control
cannot be performed by a system. To prevent data inconsistency, perform the method described in
'Prevention of 64-bit data inconsistency' or 'Data assurance by program.'
Note that, however, setting CPU number-based data assurance is required for all CPUs in a multiple CPU
system because the setting of the CPUs must be the same. (Page 153 CPU Number-Based Data
Assurance Setting)
Prevention of 64-bit data inconsistency
To prevent 64-bit data inconsistency, access the specified start address of the CPU buffer memory in multiples of four similarly
to the device to be specified.
Device
D0
4 words
(64 bits)
D4
4 words
(64 bits)
(1) and (2): The 64-bit data is assured and written to CPU buffer memory.
(3) and (4): The 64-bit data is assured and read from CPU buffer memory.
Data assurance by program
To prevent data inconsistency, set a device for interlock when accessing CPU buffer memory.
Memory
CPU buffer memory
Fixed scan communication area
12 BUS ACCESS FUNCTION
122
12.2 Data Communication Between CPU Modules
CPU No.1
CPU buffer memory
G2048
(1)
G2052
(2)
G2056
Description
A program reads data in order from the start address of the CPU buffer memory (excluding the refresh area). For the
write instruction, a program writes send data in order from the end address to the start address of the CPU buffer
memory (excluding the refresh area).
Therefore, data inconsistency can be prevented by setting a device for interlock at the head of data to be
communicated.
Create an interlock in the same way as when accessing CPU buffer memory.
CPU No.2
(3) Device
D100
4 words
(64 bits)
(4)
D104
4 words
(64 bits)