Mitsubishi Electric MELSEC iQ-R Series User Manual page 126

Process cpu module
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■If an interrupt factor occurs in the STOP/PAUSE status
• For I0 to I15, I28 to I31, I48, I49, and I50 to I1023
The interrupt factor that has occurred is memorized, and the corresponding interrupt program will be executed when the CPU
module switches to the RUN state and the interrupt is enabled. Even if the same interrupt factor occurs multiple times before
switching to the RUN state, it will be memorized only once.
Main routine program
High
I50 interrupt program
I100 interrupt program
CPU module
operating status
Low
(1) The second and following interrupt factors that occur while the CPU module is in the STOP state are not memorized.
(2) When interrupts are enabled by changing the operating status of the CPU module from STOP to RUN, interrupts are executed in order from I50 that has a
higher priority level.
(3) I100 is executed. (I50 is not executed for the second time.)
• For I45
The interrupt factor that has occurred is not memorized, and therefore the corresponding interrupt program will not be
executed even when the CPU module switches to the RUN state and the interrupt is enabled. The interrupt program will be
executed when the CPU module switches to the RUN state and then the first interrupt factor occurs.
Main routine program
I45 interrupt program
CPU module operating status
Mc: Multiple CPU synchronization cycle
(1) The interrupt is not executed.
(2) The interrupt is executed.
• For I44
The interrupt factor that has occurred is not memorized, and therefore the corresponding interrupt program will not be
executed even when the CPU module switches to the RUN state and the interrupt is enabled. Instead, startup of interrupt is
prepared when the CPU module switches to the RUN state and the interrupt is enabled (the interrupt program will not be
executed upon occurrence of the first interrupt factor). Then, the interrupt program will be executed during the second cycle
after the switch to the RUN state.
Main routine program
I44 interrupt program
CPU module operating status
Sc: Inter-module synchronization cycle
(1) The interrupt is not executed.
(2) The interrupt is executed.
8 RUNNING A PROGRAM
124
8.7 Interrupt Program
Interrupts are disabled.
(DI)
I100
I50
I100
I50
×
×
(2)
STOP/PAUSE
I45
I45
I45
I45
Mc
(1)
(2)
STOP/PAUSE
I44
I44
Sc
(1)
(1)
STOP/PAUSE
EI execution
Interrupts are enabled.
(EI)
(1)
(3)
RUN
I45
I45
Mc
(2)
RUN
t
I44
Sc
(2)
RUN
t
t

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