Sfc Information; System Clock; Fixed Scan Function Information - Mitsubishi Electric MELSEC iQ-R Series User Manual

Process cpu module
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SFC information

The following is the special register area relating to SFC information.
No.
Name
SD329
Online change (SFC
block) target block
*1
number
*1 There are restrictions on the firmware version of the CPU module and software version of the engineering tool. ( Page 747 Added
and Enhanced Functions)

System clock

The following is the list of special register areas relating to the system clock.
No.
Name
SD412
One second counter
SD414
2n second clock setting
SD415
2n ms clock setting
SD420
Scan counter

Fixed scan function information

The following is the list of special register areas relating to the fixed scan function information.
No.
Name
SD480
Number of cycle overrun
events for inter-module
synchronization cycle
program (I44)
SD481
Number of cycle overrun
events for multiple CPU
synchronization program
(I45)
SD484
Number of execution
section excess errors for
multiple CPU
synchronization interrupt
program
SD500
Execution program
number
APPX
684
Appendix 5 List of Special Register Areas
Data stored
Details
SFC block number
Data stored
Details
The number of counts that is
counted once per second.
Unit setting for 2n second
clock
Unit setting for 2n ms clock
The number of counts that is
counted once for each scan.
Data stored
Details
0: No cycle overrun event
The number of events in which the inter-module synchronous
1 to 65535: Accumulated
interrupt program (I44) has not been completed within the inter-
number of cycle overrun
module synchronization cycle or the program cannot be
events
executed due to various reasons, such as execution of a higher-
priority interrupt program and interrupt disabling by the
instruction execution is stored. When the count exceeds 65535,
it returns to 0 and starts a new cycle. The number of cycle
overrun events is counted regardless of the setting content for
the error check setting of the RAS setting (execution check of
the inter-module synchronous interrupt (I44)).
0: No cycle overrun event
The number of events in which the multiple CPU
1 to 65535: Accumulated
synchronization program (I45) has not been completed within
number of cycle overrun
the fixed scan communication cycle or the program cannot be
events
executed due to various reasons, such as execution of a higher-
priority interrupt program and interrupt disabling by the
instruction execution is stored. When the count exceeds 65535,
it returns to 0 and starts a new cycle. The number of cycle
overrun events is counted regardless of the setting content for
the error check setting of the RAS setting (execution check of
the multiple CPU synchronization program (I45)).
0: No error (Normal)
The number of events in which the program is executed
1 to 65535: Accumulated
exceeding the program execution section within the specified
number of errors
multiple CPU synchronization cycle is stored. When the count
exceeds 65535, it returns to 0 and starts a new cycle. Note that
the number of error occurrences is counted regardless of the
CPU module operation setting for error detections within the
RAS setting of the CPU parameter.
Execution program number
The program number which is currently executed is stored as a
BIN value.
• A target SFC block number is stored while the online change
(SFC block) is being executed (SM329 = ON).
• FFFFH is stored when the online change (SFC block) is not
executed.
• The value in this register increments by one for each second
after the CPU module enters in RUN mode.
• A counting cycle from 0 to 65535 to 0 is repeated.
• The n value of the 2n second clock is stored (Default: 30).
• Configurable range is -32768 to 32767 (0 to FFFFH).
• The n value for the 2n ms clock is stored. (Default: 30).
• Configurable range is -32768 to 32767 (0 to FFFFH).
• The value in this register increments by one for each scan
after the CPU module enters in RUN mode (however, the
count is skipped for scans by the initial execution type
program).
• A counting cycle from 0 to 65535 to 0 is repeated.
Set by (setting
timing)
S (Status change)
Set by (setting
timing)
S (Status change)
U
U
S (Every END)
Set by (setting
timing)
S (Status change)
S (Status change)
S (Status change)
S (Status change)

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