Mitsubishi Electric MELSEC iQ-R Series User Manual page 347

■Avoidance of 64-bit data inconsistency
To avoid 64-bit data inconsistency, access the CPU buffer memory by specifying the start address as a multiple of four
similarly to the device to be specified.
Device
D0
4 words (64 bits)
D4
4 words (64 bits)
(1) The CPU module assures a 64-bit data and write the data to the CPU buffer memory. (TO U3E0 K2052 D0 K4)
(2) The CPU module assures a 64-bit data and write the data to the CPU buffer memory. (TO U3E0 K2056 D4 K4)
(3) The CPU module assures a 64-bit data and read the data from the CPU buffer memory. (FROM U3E0 K2052 D100 K4)
(4) The CPU module assures a 64-bit data and read the data from the CPU buffer memory. (FROM U3E0 K2056 D104 K4)
CPU No.1
CPU buffer memory
G2048
(1)
G2052
(2)
G2056
CPU No.2
Device
(3)
D100
4 words (64 bits)
(4)
D104
4 words (64 bits)
23 MULTIPLE CPU SYSTEM FUNCTION
23.4 Data Communication Between CPU Modules
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