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BCRL—Bus Control Register L
Bit
7
—
Initial value
0
R/W
Read/Write
RAMER—RAM Emulation Register
Bit
7
—
Initial value
0
Read/Write
R
RAM Select
0
1
6
5
—
—
0
0
R/W
—
6
5
—
—
0
0
R
R/W
Flash Memory Area Selection
Addresses
H'FFE000–H'FFE3FF
H'000000–H'0003FF
H'000400–H'0007FF
H'000800–H'000BFF
H'000C00–H'000FFF
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
H'FED5
4
3
—
—
0
1
R/W
R/W
Wait Enable
Wait input by WAIT pin disabled.
0
WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
1
Write Data Buffer Enable
0
Write data buffer function not used
1
Write data buffer function used
H'FEDB
4
3
—
RAMS
0
0
R/W
R/W
Block Name
RAM area 1 kB
EB0 (1 kB)
EB1 (1 kB)
EB2 (1 kB)
EB3 (1 kB)
Bus Controller
2
1
—
WDBE
WAITE
0
0
R/W
R/W
Flash Memory
2
1
RAM2
RAM1
RAM0
0
0
R/W
R/W
RAMS
RAM2
RAM1
0
*
*
1
0
0
1
1
0
1
*: Don't care
0
0
R/W
0
0
R/W
RAM0
*
1007
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