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Bit 12—Receive Overload Warning Interrupt Mask: Enables or disables error warning
interrupt requests caused by the receive error counter.
Bit 12: IMR4
0
1
Bit 11—Transmit Overload Warning Interrupt Mask: Enables or disables error warning
interrupt requests caused by the transmit error counter.
Bit 11: IMR3
0
1
Bit 10—Remote Frame Request Interrupt Mask: Enables or disables remote frame reception
interrupt requests.
Bit 10: IMR2
0
1
Bit 9—Receive Message Interrupt Mask: Enables or disables message reception interrupt
requests.
Bit 9: IMR1
0
1
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
Bit 4—Bus Operation Interrupt Mask: Enables or disables interrupt requests due to bus
operation in sleep mode.
Bit 4: IMR12
0
1
Description
REC error warning interrupt request to CPU by IRR4 enabled
REC error warning interrupt request to CPU by IRR4 disabled (Initial value)
Description
TEC error warning interrupt request to CPU by IRR3 enabled
TEC error warning interrupt request to CPU by IRR3 disabled (Initial value)
Description
Remote frame reception interrupt request to CPU by IRR2 enabled
Remote frame reception interrupt request to CPU by IRR2 disabled
Description
Message reception interrupt request to CPU by IRR1 enabled
Message reception interrupt request to CPU by IRR1 disabled (Initial value)
Description
Bus operation interrupt request to CPU by IRR12 enabled
Bus operation interrupt request to CPU by IRR12 disabled
(Initial value)
(Initial value)
553
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