Input Sampling And A/D Conversion Time - Hitachi H8S/2646 Hardware Manual

16.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D
D
conversion timing. Table 16-4 indicates the A/D conversion time.
As indicated in figure 16-5, the A/D conversion time includes t
length of t varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 16-4.
In scan mode, the values given in table 16-4 apply to the first conversion time. The values given
in table 16-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give a conversion time of at least 10 µs.
ø
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
(2)
t
D
t
SPL
t
CONV
602
(1)
(2)
t
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
Figure 16-5 A/D Conversion Timing
and the input sampling time. The
D
t
SPL
t
CONV