Hitachi H8S/2646 Hardware Manual page 908

MRB—DTC Mode Register B
Bit 7
CHNE
Initial value Undefined
Read/Write —
DTC Chain Transfer Enable
0 End of DTC data transfer
1 DTC chain transfer
SAR—DTC Source Address Register
Bit 23
Initial value
Unde-
fined
Read/Write —
DAR—DTC Destination Address Register
Bit 23
Initial value
Unde-
fined
Read/Write —
876
6 5
DISEL —
Undefined Undefined
— —
DTC Interrupt Select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is
enabled
22 21 20 19
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
Specify DTC transfer data source address
22 21 20 19
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
Specify DTC transfer data destination address
H'EBC0–H'EFBF
4 3
— —
Undefined Undefined Undefined
— —
H'EBC0–H'EFBF
- - -
- - -
- - -
- - -
H'EBC0–H'EFBF
- - -
- - -
- - -
- - -
2 1 0
— — —
Undefined Undefined
— — —
4 3 2 1
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
4 3 2 1
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
DTC
DTC
0
Unde-
fined
—
DTC
0
Unde-
fined
—