Pwm Duty Registers 1A, 1C, 1E, 1G (Pwdtr1A, 1C, 1E, 1G) - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G)

Initial value

There are four PWDTR1x registers (PWDTR1A, 1C, 1E, 1G). PWDTR1A is used for outputs

PWM1A and PWM1B, PWDTR1C for outputs PWM1C and PWM1D, PWDTR1E for outputs

PWM1E and PWM1F, and PWDTR1G for outputs PWM1G and PWM1H.

PWDTR1 cannot be read or written to directly. When a PWCYR1 compare match occurs, data is

transferred from buffer register 1 (PWBFR1) to PWDTR1.

PWDTR1x is initialized to H'EC00 when the counter start bit (CST) in PWCR1 is cleared to 0,

and also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and

module stop mode.

Bits 15 to 13—Reserved: These bits cannot be read from or written to.

Bit 12—Output Terminal Select (OTS): Bit 12 selects the pin used for PWM output according

to the value in bit 12 in the buffer register that is transferred by a PWCYR1 compare match.

Unselected pins output a low level (or a high level when the corresponding bit in PWPR1 is set to

Bits 11 and 10—Reserved: These bits cannot be read from or written to.

Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0

in the buffer register that is transferred by a PWCYR1 compare match. A high level (or a low level

when the corresponding bit in PWPR1 is set to 1) is output from the time PWCNT1 is cleared by a

PWCYR1 compare match until a PWDTR1 compare match occurs. When all the bits are 0, there

— DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0

PWM1A output selected

PWM1B output selected

PWM1C output selected

PWM1D output selected

PWM1E output selected

PWM1F output selected

PWM1G output selected

PWM1H output selected

(Initial value)