When Instruction Execution Is Delayed By One State - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

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When Instruction Execution is Delayed by One State

Caution is required in the following cases, as instruction execution is one state later than usual.

1. When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a

one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on-

chip ROM or RAM is always delayed by one state.

2. When break interruption by instruction fetch is set, the set address indicates on-chip ROM or

RAM space, and that address is used for data access, the instruction that executes the data

access is one state later than in normal operation.

3. When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction has one of the addressing

modes shown below, and that address indicates on-chip ROM or RAM, and that address is

used for data access, the instruction will be one state later than in normal operation.

@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),

@(d:16,PC), @@aa:8

4. When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction is NOP or SLEEP, or has

#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the

instruction will be one state later than in normal operation.