Hitachi H8S/2646 Hardware Manual page 291

Table 9-13 PA7 to PA4 Pin Functions
Pin
H8S/2646 PA7/A23
H8S/2646R /SEG24 to
H8S/2645 PA4/A20
/SEG21
H8S/2648 PA7/A23
H8S/2648R /SEG40 to
H8S/2647 PA4/A20
/SEG37
Table 9-14 PA3 to PA0 Pin Functions
Pin Selection Method and Pin Functions
PA3/A19/COM4 to Switches as follows according to the combinations of bits SGS3 to SGS0 of
PA0/A16/COM1 LCD driver LPCR, bits AE3 to AE0 of PFGR, and bits PA3DDR to PA0DDR of
PADDR.
Setting of
SGS3 to SGS0
Operating
mode
Setting of AE3
to AE0
PAnDDR
Pin function
Selection Method and Pin Functions
Switches as follows according to the combinations of bits SGS3 to SGS0 of LCD
driver LPCR, bits AE3 to AE0 of PFGR, and bits PA7DDR to PA4DDR of PADDR.
Setting of
SGS3 to SGS0
Operating
mode
Setting of AE3 Address
to AE0 output
enabled
PAnDDR —
Pin function A23 to
A20
output
Address
output
enabled
—
A19 to
A16
output
Port
Modes 4 to 6
Address output
disabled
0 1
PA7 to PA7 to PA7 to
PA4 PA4 PA4
input output input
0000
Modes 4 to 6
Address output
disabled
0 1
PA3 to PA3 to
PA0 input PA0
output
SEG output
H8S/2646,
H8S/2646R,
H8S/2645
Mode 7 —
— —
0 1 —
PA7 to SEG24 to
PA4 SEG21
output output
Mode 7
—
0 1
PA3 to PA3 to
PA0 input PA0
output
H8S/2648,
H8S/2648R,
H8S/2647
—
—
—
SEG40 to
SEG37
output
n = 7 to 4
Other than
0000
—
—
—
COM1 to
COM4
output
n = 3 to 0
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