Hitachi H8S/2646 Hardware Manual page 918

Bit 7
—
Initial value 0
Read/Write —
Unread Interrupt Flag
0
1
Bus Operation Interrupt Flag
0 CAN bus idle state
[Clearing condition]
Writing 1
1 CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
Note: * Only 1 can be written, to clear the flag.
886
6 5
— —
0 0
— —
Mailbox Empty Interrupt Flag
0 [Clearing condition]
Writing 1
1 Transmit message has been transmitted or aborted, and new message
can be stored
[Setting condition]
When TXPR (transmit wait register) is cleared by completion of
transmission or completion of transmission abort
[Clearing condition]
Clearing of all bits in UMSR (unread message status register)
Unread message overwrite
[Setting condition]
When UMSR (unread message status register) is set
4 3
IRR12 —
0 0
R/(W)* —
2 1 0
— IRR9 IRR8
0 0 0
— R/(W)* R/(W)*