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15.2.6
Transmit Wait Cancel Register (TXCR)
The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls
cancellation of transmit wait messages in mailboxes (buffers).
TXCR
Bit:
Initial value:
R/W:
Bit:
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9
Initial value:
R/W:
Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register: These bits control cancellation of
transmit wait messages in the corresponding HCAN mailboxes.
Bit x: TXCRx
0
1
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
542
15
14
TXCR7
TXCR6
TXCR5
0
0
R/W
R/W
7
6
0
0
R/W
R/W
Description
Transmit message cancellation idle state in corresponding mailbox
[Clearing condition]
Completion of TXPR clearing (when transmit message is canceled normally)
TXPR cleared for corresponding mailbox (transmit message cancellation)
13
12
11
TXCR4
TXCR3
0
0
R/W
R/W
R/W
5
4
0
0
R/W
R/W
R/W
10
9
TXCR2
TXCR1
0
0
0
R/W
R/W
3
2
1
0
0
0
R/W
R/W
8
—
0
—
0
TXCR8
0
R/W
(Initial value)
(x = 15 to 0)
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