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Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode.
With a quartz oscillator (table 22-5), select a wait time of 8ms (oscillation stabilization time) or
more, depending on the operating frequency. With an external clock, there are no specific wait
requirements.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode, watch mode, and when making a direct transition.
Bit 3
OPE
Description
0
In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signals are high-impedance.
1
In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained.
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
Description
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
(Initial value)
(Initial value)
731
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