Hitachi H8S/2646 Hardware Manual page 869

Instruction Mnemonic
XOR XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XORC XORC #xx:8,CCR
XORC #xx:8,EXR
Notes: *1 An internal operation may require between 0 and 3 additional states, depending on the
preceding instruction.
*2 When n bytes of data are transferred.
*3 2 when EXR is invalid, 3 when EXR is valid.
*4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Branch
Instruction Address
Fetch Read
I J
1
1
2
1
3
2
1
2
Byte Word
Stack Data Data
Operation Access Access
K L M
Internal
Operation
N
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