Register Configuration; Register Descriptions; System Control Register (Syscr) - Hitachi H8S/2646 Hardware Manual

19.1.2

Register Configuration

The on-chip RAM is controlled by SYSCR. Table 19-1 shows the address and initial value of
SYSCR.
Table 19-1 RAM Register
Name
System control register
Note: * Lower 16 bits of the address.
19.2

Register Descriptions

19.2.1

System Control Register (SYSCR)

Bit : 7
MACS
Initial value : 0
R/W : R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
654
Abbreviation
SYSCR
6 5 4
— INTM1 INTM0
0 0 0
— R/W R/W
R/W Initial Value
R/W H'01
3 2
NMIEG —
0 0
R/W R/W
Address*
H'FDE5
1 0
— RAME
0 1
— R/W
(Initial value)