Dtc Transfer Count Register B (Crb); Dtc Enable Registers (Dtcer) - Hitachi H8S/2646 Hardware Manual

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
8.2.6

DTC Transfer Count Register B (CRB)

Bit : 15 14
Initial value :
*
— —
R/W :
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7

DTC Enable Registers (DTCER)

Bit : 7
DTCE7
Initial value : 0
R/W : R/W
The DTC enable registers comprise eight 8-bit readable/writable registers, DTCERA to DTCERG
and DTCERI, with bits corresponding to the interrupt sources that can control enabling and
disabling of DTC activation. These bits enable or disable DTC service for the corresponding
interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
188
13 12 11 10
* * * *
— — — —
6 5
DTCE6 DTCE5
0 0
R/W R/W
9 8 7
* * * *
— — — —
4 3
DTCE4 DTCE3
0 0
R/W R/W
6 5 4 3
* * * *
— — — —
2 1
DTCE2 DTCE1
0 0
R/W R/W
2 1 0
* * *
— —
*: Undefined
0
DTCE0
0
R/W