Hitachi H8S/2646 Hardware Manual page 25

12.1.4 Register Configuration.......................................................................................... 416
12.2 Register Descriptions ......................................................................................................... 417
12.2.1 Timer Counter (TCNT)......................................................................................... 417
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 417
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 422
12.2.4 Notes on Register Access...................................................................................... 423
12.3 Operation............................................................................................................................ 425
12.3.1 Watchdog Timer Operation .................................................................................. 425
12.3.2 Interval Timer Operation ...................................................................................... 427
12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 427
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 428
12.4 Interrupts ............................................................................................................................ 429
12.5 Usage Notes ....................................................................................................................... 429
12.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 429
12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 430
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 430
12.5.4 Internal Reset in Watchdog Timer Mode.............................................................. 430
12.5.5 OVF Flag Clearing in Interval Timer Mode ......................................................... 430
Section 13 Serial Communication Interface (SCI) ............................................431
13.1 Overview............................................................................................................................ 431
13.1.1 Features ................................................................................................................. 431
13.1.2 Block Diagram...................................................................................................... 433
13.1.3 Pin Configuration.................................................................................................. 434
13.1.4 Register Configuration.......................................................................................... 435
13.2 Register Descriptions ......................................................................................................... 436
13.2.1 Receive Shift Register (RSR) ............................................................................... 436
13.2.2 Receive Data Register (RDR)............................................................................... 436
13.2.3 Transmit Shift Register (TSR).............................................................................. 437
13.2.4 Transmit Data Register (TDR).............................................................................. 437
13.2.5 Serial Mode Register (SMR) ................................................................................ 438
13.2.6 Serial Control Register (SCR) .............................................................................. 441
13.2.7 Serial Status Register (SSR) ................................................................................. 445
13.2.8 Bit Rate Register (BRR) ....................................................................................... 449
13.2.9 Smart Card Mode Register (SCMR)..................................................................... 456
13.2.10 Module Stop Control Register B (MSTPCRB) .................................................... 457
13.3 Operation............................................................................................................................ 459
13.3.1 Overview............................................................................................................... 459
13.3.2 Operation in Asynchronous Mode........................................................................ 461
13.3.3 Multiprocessor Communication Function ............................................................ 472
13.3.4 Operation in Clocked Synchronous Mode............................................................ 480
13.4 SCI Interrupts ..................................................................................................................... 488
13.5 Usage Notes ....................................................................................................................... 489
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