Bus Timing - Hitachi H8S/2646 Hardware Manual

23.4.3

Bus Timing

Table 23-6 lists the bus timing.
Table 23-6 Bus Timing
Condition : V = PWMV
CC
V = 4.5 V to AV
ref
+75°C (regular specifications), T
Item
Address delay time
Address setup time
Address hold time
AS delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 1
Read data access time 2
Read data access time 3
Read data access time 4
Read data access time 5
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
= 4.5 V to 5.5 V, LPV
CC
, V = PWMV
CC SS
a
Symbol Min
t —
AD
0.5 × t
t
– 32
AS
cyc
0.5 × t
t
– 15
AH
cyc
t —
ASD
t —
RSD1
t —
RSD2
t 20
RDS
t 10
RDH
t —
ACC1
t —
ACC2
t —
ACC3
t —
ACC4
t —
ACC5
t —
WRD1
t —
WRD2
1.0 × t
t – 40
WSW1 cyc
1.5 × t
t – 30
WSW2 cyc
t —
WDD
0.5 × t
t – 20
WDS cyc
0.5 × t
t – 10
WDH cyc
t 30
WTS
t 5
WTH
= 4.5 V to 5.5 V, AV
CC
= PLLV = AV
SS SS SS
= –40°C to +85°C (wide-range specifications)
Condition
Max
45
—
—
45
45
45
—
—
1.0 × t
– 60
cyc
1.5 × t
– 50
cyc
2.0 × t
– 60
cyc
2.5 × t
– 50
cyc
3.0 × t
– 60
cyc
35
45
—
—
45
—
—
—
—
= 4.5 V to 5.5 V,
CC
= 0 V, T = –20°C to
a
Unit Test Conditions
ns Figure 23-7 to
ns Figure 23-11
ns
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