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Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the
timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag
clearing by the DTC.
ø
Address
Write signal
Status flag
Interrupt
request
signal
Figure 10-46 Timing for Status Flag Clearing by CPU
ø
Address
Status flag
Interrupt
request
signal
Figure 10-47 Timing for Status Flag Clearing by DTC Activation
TSR write cycle
T1
T2
TSR address
DTC
read cycle
write cycle
T1
T2
T1
Destination
Source address
address
DTC
T2
375
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