Dtc Vector Register (Dtvecr) - Hitachi H8S/2646 Hardware Manual

Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn Description
0 DTC activation by this interrupt is disabled
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
1 DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
8.2.8

DTC Vector Register (DTVECR)

7
Bit :
SWDTE
Initial value : 0
R/W : R/(W)
Notes: *1 Only 1 can be written to the SWDTE bit.
*2 Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
6 5
DTVEC6 DTVEC5
0 0
*1 *2 *2
R/(W) R/(W)
4 3
DTVEC4 DTVEC3 DTVEC2
0 0
*2 *2
R/(W) R/(W) R/(W)
(Initial value)
(n = 7 to 0)
2 1 0
DTVEC1 DTVEC0
0 0 0
*2 *2
R/(W) R/(W)
*2
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