Irq Enable Register (Ier) - Hitachi H8S/2646 Hardware Manual

As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
5.2.3

IRQ Enable Register (IER)

Bit : 7
—
Initial value : 0
R/W : R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ5 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits select whether IRQ5 to
IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupts disabled
1 IRQn interrupts enabled
106
6 5
— IRQ5E IRQ4E
0 0
R/W R/W R/W
4 3 2
IRQ3E IRQ2E
0 0 0
R/W R/W
1 0
IRQ1E IRQ0E
0 0
R/W R/W
(Initial value)
(n = 5 to 0)