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9.6.2
Register Configuration
Table 9-9 shows the port 5 register configuration.
Table 9-9
Port 5 Register Configuration
Name
Port 5 data direction register
Port 5 data register
Port 5 register
Notes: *1 Lower 16 bits of the address.
*2 Value of bits 2 to 0.
Port 5 Data Direction Register (P5DDR)
Bit
:
7
—
Initial value :
Undefined Undefined Undefined Undefined Undefined
R/W
:
—
P5DDR is an 8-bit write-only register that specifies whether individual bits are input or output for
each of each of the pins in port 5. It is not possible to read it. An undefined value is returned if an
attempt is made to read it.
Setting one of the bits of P5DDR to 1 sets the corresponding pin in port 5 to output, and clearing
the bit to 0 sets the corresponding pin to input.
P5DDR is initialized to H'0 (bits 2 to 0) if a reset occurs and in the hardware standby mode. The
previous values are retained by P5DDR in the software standby mode. Since SCI is initialized in
the H8S/2648, H8S/2648R, and H8S/2647, the pin states are determined by the by the P5DDR and
P5DR settings.
Port 5 Data Register (P5DR)
Bit
:
7
—
Initial value :
Undefined Undefined Undefined Undefined Undefined
R/W
:
—
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).
250
Abbreviation
P5DDR
P5DR
PORT5
6
5
—
—
—
—
—
—
6
5
—
—
—
—
—
—
R/W
Initial Value
W
H'0
R/W
H'0
R
H'0
4
3
2
—
P52DDR P51DDR P50DDR
0
—
W
4
3
2
—
P52DR
0
—
R/W
*2
*1
Address
H'FE34
H'FF04
H'FFB4
1
0
0
0
W
W
1
0
P51DR
P50DR
0
0
R/W
R/W
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