Hitachi H8S/2646 Hardware Manual page 580

Hitachi 16-bit single-chip microcomputer h8s/2646 series
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Bit 13—Error Passive Interrupt Flag: Status flag indicating the error passive state caused by the
transmit/receive error counter.
Bit 13: IRR5
0
1
Bit 12—Receive Overload Warning Interrupt Flag: Status flag indicating the error warning
state caused by the receive error counter.
Bit 12: IRR4
0
1
Bit 11—Transmit Overload Warning Interrupt Flag: Status flag indicating the error warning
state caused by the transmit error counter.
Bit 11: IRR3
0
1
Bit 10—Remote Frame Request Interrupt Flag: Status flag indicating that a remote frame has
been received in a mailbox (buffer).
Bit 10: IRR2
0
1
548
Description
[Clearing condition]
Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
Description
[Clearing condition]
Writing 1
Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
Description
[Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
Description
[Clearing condition]
Clearing of all bits in RFPR (remote request register) of the mailbox, which
enables the receive interrupt requests in the MBIMR
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed, when corresponding
MBIMR = 0
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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