Interrupt Mask Register (Imr) - Hitachi H8S/2646 Hardware Manual

15.2.13 Interrupt Mask Register (IMR)

The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that
enable or disable requests by individual interrupt sources.
IMR
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask: Enables or disables overload
frame/bus off recovery interrupt requests.
Bit 15: IMR7
0
1
Bit 14—Bus Off Interrupt Mask: Enables or disables bus off interrupt requests caused by the
transmit error counter.
Bit 14: IMR6
0
1
Bit 13—Error Passive Interrupt Mask: Enables or disables error passive interrupt requests
caused by the transmit/receive error counter.
Bit 13: IMR5
0
1
552
15 14
IMR7 IMR6 IMR5
1 1
R/W R/W R/W
7 6
— —
1 1
— —
Description
Overload frame/bus off recovery interrupt request to CPU by IRR7 enabled
Overload frame/bus off recovery interrupt request to CPU by IRR7 disabled
Description
Bus off interrupt request to CPU by IRR6 enabled
Bus off interrupt request to CPU by IRR6 disabled
Description
Error passive interrupt request to CPU by IRR5 enabled
Error passive interrupt request to CPU by IRR5 disabled
13 12 11
IMR4 IMR3
1 1 1
R/W R/W
5 4 3
— IMR12 —
1 1 1
— R/W —
10 9
IMR2 IMR1
1 1
R/W R/W
2 1
— IMR9 IMR8
1 1
— R/W R/W
(Initial value)
(Initial value)
(Initial value)
8
—
0
—
0
1