Section 4 Exception Handling; Overview; Exception Handling Types And Priority; Exception Handling - Hitachi H8S/2646 Hardware Manual

4.1

Overview

4.1.1

Exception Handling Types and Priority

As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4-1 Exception Types and Priority
Priority Exception Type
High Reset
* 1
Trace
Direct transition
Interrupt
Low Trap instruction (TRAPA)
Notes: *1 Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
*2 Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
*3 Trap instruction exception handling requests are accepted at all times in program
execution state.

Section 4 Exception Handling

Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog overflows. The CPU enters the
reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when a direct transition occurs due to execution of a
SLEEP instruction.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued
*3
Started by execution of a trap instruction (TRAPA)
*2
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