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9.15.2
Register Configuration
Table 9-32 shows the port J register configuration.
Table 9-32 Port J Registers
Name
Port J data direction register
Port J data register
Port J register
Note: * Lower 16 bits of the address
Port J Data Direction Register (PJDDR)
Bit
:
7
PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR
Initial value :
0
R/W
:
W
PJDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port J. PJDDR cannot be read. If it is, an undefined value will be read.
PJDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port J Data Register (PJDR)
Bit
:
7
PJ7DR
Initial value :
0
R/W
:
R/W
PJDR is an 8-bit readable/writeable register that stores output data for the port J pins (PJ7 to PJ0).
PJDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
290
Abbreviation
PJDDR
PJDR
PORTJ
6
5
0
0
W
W
6
5
PJ6DR
PJ5DR
PJ4DR
0
0
R/W
R/W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
4
3
0
0
W
W
4
3
PJ3DR
PJ2DR
0
0
R/W
R/W
R/W
Address*
H'FC21
H'FC25
H'FC29
2
1
0
0
W
W
W
2
1
PJ1DR
PJ0DR
0
0
R/W
R/W
0
0
0
0
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