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5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts*.
Note: * 47 sources in the H8S/2648, H8S/2648R, and H8S/2647.
43 sources in the H8S/2646, H8S/2646R, and H8S/2645.
5.3.1
External Interrupts
There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0
can be used to restore the H8S/2646 Series from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5
to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ5 to IRQ0.
• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2.
IRQn input
Note: n = 5 to 0
Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0
IRQnSCA, IRQnSCB
Edge/level
detection circuit
Clear signal
IRQnE
IRQnF
S
Q
R
IRQn interrupt
request
109
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