Module Stop Control Register B (Mstpcrb) - Hitachi H8S/2646 Hardware Manual

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV Description
0 TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1 TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: It is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a
normal SCI, 0 should be written in this bit.
Bit 0
SMIF Description
0 Operates as normal SCI (smart card interface function disabled)
1 Smart card interface function enabled

13.2.10 Module Stop Control Register B (MSTPCRB)

Bit :
MSTPB7
Initial value :
R/W : R/W
MSTPCRB is an 8-bit readable/writable register that perform module stop mode control.
Setting any of bits MSTPB7 to MSTPB6 to 1 stops SCI0 to SCI1 operating and enter module stop
mode on completion of the bus cycle. For details, see section 22.5, Module Stop Mode.
MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
7 6 5
MSTPB6 MSTPB5
1 1 1
R/W R/W
4 3
MSTPB4 MSTPB3 MSTPB2
1 1
R/W R/W
(Initial value)
(Initial value)
2 1
MSTPB1 MSTPB0
1 1
R/W R/W R/W
0
1
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