Low-Power Control Register (Lpwrcr) - Hitachi H8S/2646 Hardware Manual

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid after recovery from software standby mode,
watch mode, or subactive mode
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0
0 0 0
1
1 0
1
1 0 0
1
1 —
21.2.2

Low-Power Control Register (LPWRCR)

Bit
DTON
Initial value
Read/Write R/W
LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The
following pertains to bits 1 and 0. For details of the other bits, see section 22.2.3, Low-Power
Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby
mode. It is not initialized in software standby mode.
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
7 6 5
LSON NESEL
0 0 0
R/W R/W
4 3
SUBSTP RFCUT
0 0
R/W R/W
(Initial value)
(Initial value)
2 1
— STC1 STC0
0 0
R/W R/W R/W
0
0
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