Sub-Active Mode; 22.10.2 Exiting Sub-Active Mode - Hitachi H8S/2646 Hardware Manual

22.10

Sub-Active Mode

22.10.1 Sub-Active Mode
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to
sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1,
a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition
is made to sub-active mode.
In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Supporting modules other than WDT0, and WDT1 are also stopped.
When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0.

22.10.2 Exiting Sub-Active Mode

Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins.
Exiting Sub-Active Mode by SLEEP Instruction: When the SLEEP instruction is executed with
the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU
exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is
executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit =
1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with
the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit =
1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0).
See section 22.11, Direct Transitions, for details of direct transitions.
Exiting Sub-Active Mode by RES Pins: For exiting sub-active mode by the RES pins, see,
Claering with the RES pins in section 22.6.2, Clearing Software Standby Mode.
Exiting Sub-Active Mode by STBY Pin: When the STBY pin level is driven Low, a transition is
made to hardware standby mode.
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