Register Descriptions; Standby Control Register (Sbycr) - Hitachi H8S/2646 Hardware Manual

22.2

Register Descriptions

22.2.1

Standby Control Register (SBYCR)

Bit :
SSBY
Initial value :
R/W : R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
control bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Bit 7
SSBY Description
0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
Shifts to sub-sleep mode when the SLEEP instruction is executed in
sub-active mode.
1 Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP
instruction is executed in high-speed mode or medium-speed mode.
Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in
sub-active mode.
730
7 6 5
STS2 STS1
0 1 0
R/W R/W
4 3
STS0 OPE
1 1
R/W R/W
2 1 0
— — —
0 0 0
— — —
(Initial value)