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Bit 1—Unread Interrupt Mask: Enables or disables unread receive message overwrite interrupt
requests.
Bit 1: IMR9
0
1
Bit 0—Mailbox Empty Interrupt Mask: Enables or disables mailbox empty interrupt requests.
Bit 0: IMR8
0
1
15.2.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
REC
Bit:
Initial value:
R/W:
15.2.15 Transmit Error Counter (TEC)
The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating the number of transmit message errors on the CAN bus. The count value is stipulated in
the CAN protocol.
TEC
Bit:
Initial value:
R/W:
554
Description
Unread message overwrite interrupt request to CPU by IRR9 enabled
Unread message overwrite interrupt request to CPU by IRR9 disabled
Description
Mailbox empty interrupt request to CPU by IRR8 enabled
Mailbox empty interrupt request to CPU by IRR8 disabled
7
6
0
0
R
R
7
6
0
0
R
R
5
4
3
0
0
0
R
R
R
5
4
3
0
0
0
R
R
R
(Initial value)
(Initial value)
2
1
0
0
0
0
R
R
R
2
1
0
0
0
0
R
R
R
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