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Bus-released state
Exception handling state
Reset state
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
Notes: *1
goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
*2
*3
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See section 22, Power-Down Modes.
2.8.2
Reset State
When the RES goes low, all current processing stops and the CPU enters the reset state. In reset
state all interrupts are disenabled.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer.
66
End of bus request
Program execution state
External interrupt request
RES= High
*1
Figure 2-15 State Transitions
Bus request
STBY= High, RES= Low
Hardware standby mode
Sleep mode
Software standby mode
*2
*3
Power-down state
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