Ppg Output Mode Register (Pmr) - Hitachi H8S/2646 Hardware Manual

11.2.6

PPG Output Mode Register (PMR)

Bit : 7
G3INV
Initial value : 1
R/W : R/W
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping
operation for each group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB
and the non-overlap margin is set in TGRA. The output values change at compare match A and B.
For details, see section 11.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output
group 3 (pins PO15 to PO12).
Bit 7
G3INV Description
0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output
group 2 (pins PO11 to PO8).
Bit 6
G2INV Description
0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
6 5
G2INV G1INV G0INV
1 1
R/W R/W
4 3
G3NOV G2NOV
1 0
R/W R/W R/W
2 1 0
G1NOV G0NOV
0 0 0
R/W R/W
(Initial value)
(Initial value)
397