General Status Register (Gsr) - Hitachi H8S/2646 Hardware Manual

Bit 1—Halt Request (MCR1): Controls halting of the HCAN module.
Bit 1: MCR1
0
1
Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module.
Bit 0: MCR0
0
1
In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the
HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0
is cleared to 0.
15.2.2

General Status Register (GSR)

The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN
bus.
GSR
Bit:
Initial value:
R/W:
Bits 7 to 4—Reserved: These bits always read 0.
536
Description
HCAN normal operating mode
HCAN halt mode transition request
Description
Normal operating mode (MCR0 = 0 and GSR3 = 0)
[Setting condition]
When 0 is written after an HCAN reset
HCAN reset mode transition request
7 6
— — —
0 0
R R
5 4 3
— GSR3
0 0 1
R R R
(Initial value)
(Initial value)
2 1
GSR2 GSR1 GSR0
1 0
R R
0
0
R