Section 13 Serial Communication Interface (Sci); Overview; Features - Hitachi H8S/2646 Hardware Manual

Section 13 Serial Communication Interface (SCI)

13.1

Overview

The H8S/2646 Series is equipped with 2 or 3 independent serial communication interface (SCI)
channels*. The SCI can handle both asynchronous and clocked synchronous serial
communication. A function is also provided for serial communication between processors
(multiprocessor communication function).
Note: * Two channels in the H8S/2646, H8S/2646R, and H8S/2645; three channels in the
H8S/2648, H8S/2648R, and H8S/2647.
13.1.1

Features

SCI features are listed below.
• Choice of asynchronous or clocked synchronous serial communication mode
Asynchronous mode
 Serial data communication executed using asynchronous system in which synchronization
is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
 A multiprocessor communication function is provided that enables serial data
communication with a number of processors
 Choice of 12 serial data transfer formats
Data length
Stop bit length
Parity
Multiprocessor bit
 Receive error detection : Parity, overrun, and framing errors
 Break detection
Clocked Synchronous mode
 Serial data communication synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
 One serial data transfer format
Data length
: 7 or 8 bits
: 1 or 2 bits
: Even, odd, or none
: 1 or 0
: Break can be detected by reading the RxD pin level directly in
case of a framing error
: 8 bits
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