Module Stop Control Register A (Mstpcra) - Hitachi H8S/2646 Hardware Manual

Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE Description
0 DTC software activation is disabled
[Clearing conditions]
•
When the DISEL bit is 0 and the specified number of transfers have not ended
•
When 0 s written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
1 DTC software activation is enabled
[Holding conditions]
•
When the DISEL bit is 1 and data transfer has ended
•
When the specified number of transfers have ended
•
During data transfer due to software activation
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
8.2.9

Module Stop Control Register A (MSTPCRA)

Bit 7
MSTPA7
Initial value 0
Read/Write R/W
MSTPCRA is a 8-bit readable/writable register that performs module stop mode control.
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus
cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6
bit while the DTC is operating. For details, see section 22.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
190
6 5
MSTPA6 MSTPA5 MSTPA4
0 1
R/W R/W
4 3
MSTPA3 MSTPA2
1 1
R/W R/W R/W
(Initial value)
2 1 0
MSTPA1 MSTPA0
1 1 1
R/W R/W